View CS98200-EB_1026702.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? copyright 2002 cirrus logic (all rights reserved) oct ?02 ds581pp2 1 http://www.cirrus.com new highly-integrated processor for tomorrow ? s dvd players and dvd receivers (cont.) cs98200 data sheet preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this pr oduct without notice. features dvd-video, vcd, vcd 2.0, svcd, cd, and other popular standards dvd-audio including cppm and verance ? watermark protection mpeg-1, mpeg-2, and leading edge mpeg-4 audio and video decoding kodak picture cd flexible atapi or av bus dvd loader support with no additional logic dual 32-bit risc processors, supported by rtos, c/c++ compilers, and source level debuggers 32-bit dsp capable of running ac-3, mpeg, dts, mp3, wma, and aac audio decode algorithms high quality integrated video encoder with six 10-bit video d/a converters component (rgb or yuv) or composite & s-video output interlaced (pal/ntsc) or progressive (480p) output, with macrovision ? copy protection ccir656 video i/o for video capture, pvr and dvr type applications, picture-in-picture support iec60958/937 (s/pdif) & simultaneous pcm output 5.1 downmix, karaoke echo mix, pitch shift, and many other effects pal / ntsc transcoding dual 16550 compatible uarts atapi/ ide interface for hard disk, audio server, and personal video recorder (pvr) applications 240-pin mqfp package ordering information: cs98200-cm see ordering information legend on page 60 . overview cs98200 is a highly-integrated processor that provides all of the audio and video processing functions needed for the next generation of feature-rich dvd players, dvd receivers and internet dvd applications. tomorrow's features available today in a single chip solution are dvd-audio, mp3, wma ? , mpeg-2/4: aac, kodak picture cd ? , dolby digital ? , dolby prologic ii ? , and dts digital surround ? decoding. it supports most popular cd formats, dvd navigation, disk control, video decoding and up to eight channels of audio output. an extension of cirrus' cs98000 dvd product line, the cs98200 integrates six 10-bit video digital-to-analog converters (dacs) and tv encoding with progressive scan functionality. progressive scan video provides high resolution and eliminates the "flickering" effect present in traditional video playback. other features enabled by this integrated chip include karaoke functionality and video special effects. its extended feature set makes it ideal for your next innovative dvd application ? today. need to get your product to market quickly? cirrus' total entertainment platform solutions include dvd front-end controllers, mpeg encoders, audio dsps, and digital power amplifiers ? everything you need to launch your product before the competition. cs98200 is a cirrus total entertainment total-e ? ic solution specifically designed for consumer entertainment electronics.
2 ? copyright 2002 cirrus logic (all rights reserved) ds581pp2 cs98200 next generation dvd processor overview (cont.) here is a summary of the cs98200 features. system characteristics dual 32-bit (180 mhz) risc processors 32-bit dsp processor ~ 180 mips 240-pin mqfp package all i/o pins are 3 v with 5 v tolerance advanced 0.18 cmos technology low power modes and clock shutoff memory controller up to 120 mhz sdram from 4 mb to 32 mb flash databus isolated from sdram bus to allow faster sdram access 32-bit data bus for dram, 8-bit data bus for rom data flow engine two dma controllers ? local memory based and direct memory-to-memory dma to/from main ram into local sram mpeg video decoder dvd, vcd, vcd 2.0 and svcd mpeg-1, mpeg-2, and mpeg-4 simple profile anti-tearing logic controls picture decode and presentation advanced error concealment hardware audio interface 8 channels pcm output at 24-bits/192 khz output rate 2 channels i2s input at 24-bits/96 khz iec 60958/61937 capabilities external interface serial master/slave ports for controlling dvd device atapi/ide interface can also control hard disk drives for pvr features programmable bidirectional i/o pins all pins not used for other functions can be reassigned as general purpose i/o pins hardware assisted support for infrared remote devices, such as remote control, infrared keyboard, mouse, printer, and more programmable parallel host master interface supports formats including atapi, isa, and more i/o channel interface supports all dvd loader protocols video processor osd module with multiple regions and transparencies full screen graphics module, with 16 bit true-color graphics plane high quality video scaling using multi-tap programmable vertical and horizontal filters video encoder six 10-bit video dac's, drives 37.5 ? load directly progressive (480p) or interlaced pal (b, d, g, h, i, n, m, 60) and ntsc mode output component (rbg or yuv) or composite + s-video output macrovision ? 7.1 support (interlaced) and macrovision ? 1.03 support (progressive) wide-screen signaling support (interlaced and progressive) and cgms closed captioning support
ds581pp2 ? copyright 2002 cirrus logic (all rights reserved) 3 cs98200 next generation dvd processor risc 0 risc 1 dsp audio interface instruction cache data cache cpu pipe mac instruction cache data cache mac cpu pipe cpu/mac instruction cache x,y data memory pcm out pcm in spdif out dvd loader i/o mpeg decoder vlc parser motion comp idct ram dvd custom loader parallel/serial data serial control atapi/generic parallel bus interface host bus i/o dataflow engine system controls ntsc/pal encoder video processor subpicture sram + cpu if system sync simple i/o dram controller video capture graphics dma (rd + wr) flash memory.control stc schedule dma(2)t sram buffer decryption misc. register banks interrupt pll pll timers digital encoding 3 dacs 3 dacs 32 kbyte internal sram arbiter + control dma decode r scaler line buffer on screen display overlay main video scaling and display picture in picture overlay line buffer / flicker filter main graphics decoder fifo sdram control video mixing dual uart pwm semi-dac 2-w ire serial (i 2 c) 3/4 w ire serial (spi) program m able i/o infrared input pll mpeg4 video decoder accelerator cpu interface alu + logic block diagram
4 ? copyright 2002 cirrus logic (all rights reserved) ds581pp2 cs98200 next generation dvd processor table of contents 1. characteristics and specifications ........................................................................8 1.1 ac and dc parametric specifications ...............................................................................8 1.1.1 absolute maximum rating ....................................................................................8 1.1.2 recommended operating conditions ...................................................................8 1.1.3 electrical characteristics ......................................................................................8 2. timings ................................................................................................................... ............... 10 2.1 timing diagram conventions ...........................................................................................10 2.2 dc characteristics ........................................................................................................ ... 11 2.2.1 atapi interface ................................................................................................... 11 2.2.2 dvd loader interface ......................................................................................... 12 2.2.3 dvd serial interface timing ................................................................................ 15 2.2.4 sdram interface ................................................................................................ 16 2.2.5 rom/nvram interface ....................................................................................... 18 2.2.6 digital video output interface ............................................................................. 20 2.2.7 video input interface ........................................................................................... 21 2.2.8 audio input interface timing ............................................................................... 22 2.2.9 audio output interface timing ............................................................................. 23 2.2.10 miscellaneous timings ...................................................................................... 24 3. typical application ....................................................................................................... .25 4. cs98200 device summary ................................................................................................ 26 4.1 block diagram ............................................................................................................. ..... 26 contacting cirrus logic support for all product questions and inquiries contact a cirrus logic sales representative. to find one nearest you go to http://www.cirrus.com/corporate/contacts/sales.cfm important notice ?preliminary? product information describes products that are in production, but for which full characterization data is not ye t available. ?advance? product information describes products that are in development and subject to development changes. cirrus logic, inc. and its subsidiaries (?cirrus ?) believe that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided ?as is? wi t hout warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information to verify, before placing orders, that inf ormation being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. no responsibility is assumed by cirrus for the use of this information, including use of this info r mation as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furn i shing this information, cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property ri ghts. cirrus owns the copyrights of the infor- mation contained herein and gives consent for copies to be made of the information only for use within your organization with r espect to cirrus integrated circuits or other parts of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promoti onal purposes, or for creating any work for resale. an export permit needs to be obtained from the competent authorities of the japanese government if any of the products or techn o logies described in this material and controlled under the ?foreign exchange and foreign trade law? is to be exported or taken out of japan. an export license and/or quota needs to be obtained from the competent authorities of the chinese government if any of the products or technologies described in this material is subject to the prc foreign trade law and is to be exported or taken out of the prc. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (?critical applications?). cirrus products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of cirrus products in such applications is und er- stood to be fully at the customer's risk. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names i n this document may be trademarks or service marks of their respective owners. purchase of i 2 c components of cirrus logic, inc., or one of its sublicensed associated companies conveys a license under the phillips i 2 c patent rights to use those com- ponents in a standard i 2 c system microsoft ? and windows media technology ? are registered trademarks or trademarks of microsoft, inc. in the united states and/or other countries. . hdcd ? , high definition compatible digital ? and pacific microsonics ? inc. are either registered trademarks or trademarks of pacific microsonics inc. in the united states and/or other countries. hdcd technology provided under license from pacific microsonics inc. this products design (and/or software) is covered by one or more of the following: 5,479,168; 5,638,074; 5,640,161; 5,808,574; 5,838,274; 5,854,600; 5,864,311; 5,872,531 with other patents pending. dolby digital, ac-3, dolby pro logic, dolby pro logic ii, dolby surround, surround ex, virtual dolby digital and the ?aac? logo are trademarks and the ?dolby digital? logo, ?dolby digital with pro logic ii? logo, ?dolby? and the double-?d? symbol are registered trademarks of dolby laboratories licensing corporation. dts, dts digital surround, dts-es extended surround, dts neo:6, and dts virtual 5.1 are trademarks and the ?dts?, ?dts-es?, ?dts virtual 5.1? lo gos are registered trademarks of the digital theater systems corporation. the ?mpeg logo? is a registered trademark of philips electronics n. v. home thx cinema and thx are registered trademarks of lucasfilm ltd. surround ex is a jointly developed technology of thx and dolby labs, inc. aac (advanced audio coding) is an ?mpe g -2-standard-based? digital audio compression algorithm (offering up 5.1 discrete decoded channels for this implementation) collaboratively developed by at&t, th e fraunhofer institute, dolby laborato- ries, and the sony corporation. in regards to the mp3 capable functionality of the cs98xxx family dsp (via downloading of mp3_4 9 3xxx_vv.ld and mp3e_493xxx_vv.ld application codes) the following statements are applicable: ?supply of this product conveys a license for personal, private and non-commercial use. mpeg layer iii audio decoding technology licensed from fraunhofer iis and thomson multimedia.?
ds581pp2 ? copyright 2002 cirrus logic (all rights reserved) 5 cs98200 next generation dvd processor 4.2 cs98200 device details .................................................................................................. 26 4.2.1 risc-32 processors ........................................................................................... 26 4.2.2 powerful 24/32-bit dsp ...................................................................................... 26 4.2.3 system controls .................................................................................................. 26 4.2.4 memory controller .............................................................................................. 26 4.2.5 data flow engine ................................................................................................ 27 4.2.6 mpeg video decoder ......................................................................................... 27 4.2.7 system synchronization ..................................................................................... 27 4.2.8 audio interface .................................................................................................... 27 4.2.9 video input .......................................................................................................... 27 4.2.10 external interface .............................................................................................. 27 4.2.11 video processor ................................................................................................ 27 4.2.12 sub-picture processor ...................................................................................... 27 4.2.13 graphics engine ............................................................................................... 27 4.2.14 on screen display module ............................................................................... 28 4.2.15 dvd loader interface ....................................................................................... 28 4.2.16 cpu interface and sram controller ................................................................ 28 4.2.17 host bus interface ............................................................................................ 28 4.2.18 video encoder .................................................................................................. 28 4.2.19 system functions ............................................................................................. 28 5. functi onal description ............................................................................................... 29 5.1 risc processor ............................................................................................................ ... 29 5.2 dsp processor ............................................................................................................. ... 29 5.3 memory control ............................................................................................................ ... 29 5.4 dataflow control (dma) ................................................................................................... 2 9 5.5 system control functions ............................................................................................... 29 5.6 dvd/atapi interface ....................................................................................................... 30 5.7 serial dvd interface ...................................................................................................... .. 30 5.8 mpeg video decoding .................................................................................................... 30 5.9 audio processing .......................................................................................................... ... 30 5.10 video encoder with progressive video dacs ............................................................... 32 5.11 video input/output interface .......................................................................................... 33 5.12 universal asynchronous receiver/transmitters (uarts) ............................................. 34 6. memory map ................................................................................................................ ....... 35 6.1 processor memory map .................................................................................................. 35 7. 240-pin mqfp pin description ....................................................................................... 36 7.1 240-pin mqfp pin layout ............................................................................................... 36 7.2 240-pin mqfp pin summary .......................................................................................... 37 7.3 pin configuration summary ............................................................................................. 37 7.4 explanation of pin types ................................................................................................. 3 8 7.5 240-pin mqfp pin assignments ..................................................................................... 38 8. interface descriptions ................................................................................................ 49 8.1 sdram interface pins ..................................................................................................... 4 9 8.2 rom/nvram interface pins ........................................................................................... 49 8.3 video output interface pins ............................................................................................. 50 8.4 video input inter face pins ............................................................................................... 50 8.5 audio pcm interface pins ............................................................................................... 51 8.6 host master/atapi interface ........................................................................................... 52 8.7 dvd loader interface ...................................................................................................... 53 8.8 dvd serial data interface ............................................................................................... 53 8.9 spi interface ............................................................................................................. ....... 54 8.10 general purpose input/output (gpio) .......................................................................... 54 8.11 uart interface pins ...................................................................................................... 55 8.12 i 2 c interface .................................................................................................................. 5 5 8.13 miscellaneous interface pins ......................................................................................... 55
6 ? copyright 2002 cirrus logic (all rights reserved) ds581pp2 cs98200 next generation dvd processor 8.14 power and ground ......................................................................................................... 56 9. 240-pin mqfp package spe cifications ...................................................................... 57 10. conventions .............................................................................................................. ...... 58 10.1 acronyms and abbreviations ......................................................................................... 58 10.2 units of measurement .................................................................................................... 5 9 10.3 general conventions ..................................................................................................... 5 9 10.4 pin description conventions .......................................................................................... 60 11. ordering information legend ................................................................................. 60 list of figures figure 1. legend for timing diagrams .......................................................................................... 1 0 figure 2. atapi interface timing diagram....................................................................................11 figure 3. dvd loader host interface ............................................................................................ 12 figure 4. dvd loader data interface ............................................................................................ 13 figure 5. dvd loader cd interface .............................................................................................. 13 figure 6. dvd loader cd interface formats ................................................................................ 14 figure 7. dvd serial interface timing.......................................................................................... .15 figure 8. sdram refresh transaction ......................................................................................... 16 figure 9. sdram burst write transaction....................................................................................16 figure 10. sdram burst read transaction.................................................................................. 17 figure 11. sdram timing........................................................................................................ ..... 17 figure 12. rom/nvram reading timing..................................................................................... 18 figure 13. rom/nvram write timing.......................................................................................... 19 figure 14. cs98200 digital video interface timing diagram ........................................................ 20 figure 15. video input timing .................................................................................................. .....21 figure 16. audio input timings................................................................................................. ..... 22 figure 17. digital audio out timing diagram ................................................................................ 23 figure 18. miscellaneous timings ............................................................................................... .. 24 figure 19. cs98200 typical application ....................................................................................... 25 figure 20. cs98200 block diagram .............................................................................................. 2 6 figure 21. video dac connections............................................................................................... 32 figure 22. uart data transfer.................................................................................................. ... 34 figure 23. 240-pin mqfp pin layout............................................................................................ 3 6 figure 24. 240-pin mqfp pinout summary .................................................................................. 37 figure 25. 240-pin mqfp package drawing ................................................................................ 57 list of tables table 1. atapi interface characteristics ...................................................................................... 1 1 table 2. sdram interface characteristics....................................................................................16 table 3. ram/nvrom characteristics ......................................................................................... 18 table 4. cs98200 digital video interface characteristics............................................................. 20 table 5. video input interface symbols and characterization data .............................................. 21 table 6. audio input interface symbols and characterization data .............................................. 22 table 7. digital audio out characteristics ..................................................................................... 23 table 8. miscellaneous timing characteristics ............................................................................. 24 table 9. memory map-risc0 processor....................................................................................... 35 table 10. host debug port address map...................................................................................... 35 table 11. dsp address map ...................................................................................................... ...35 table 12. pin configuration summary...........................................................................................3 7 table 13. pin type legend ...................................................................................................... ..... 38 table 14. 240-pin mqfp pin assignments ................................................................................... 38
ds581pp2 ? copyright 2002 cirrus logic (all rights reserved) 7 cs98200 next generation dvd processor table 15. sdram interface pins ................................................................................................. .49 table 16. rom/nvram interface................................................................................................. 4 9 table 17. video output interface ............................................................................................... ... 50 table 18. video input interface ................................................................................................ ..... 50 table 19. pcm audio interface .................................................................................................. ... 51 table 20. host master/atapi interface ........................................................................................ 52 table 21. dvd i/o channel interface ........................................................................................... 5 3 table 22. spi interface ........................................................................................................ ......... 54 table 23. general purpose i/o interface ...................................................................................... 54 table 24. uart interface pins .................................................................................................. ... 55 table 25. i 2 c interface pins.......................................................................................................... 55 table 26. miscellaneous interface pins ........................................................................................ 5 5 table 27. power and ground ..................................................................................................... ... 56 table 28. acronyms and abbreviations ........................................................................................ 58 table 29. units of measurement ................................................................................................. .. 59 table 30. pin description conventions ......................................................................................... 6 0
8 ? copyright 2002 cirrus logic (all rights reserved) ds581pp2 cs98200 next generation dvd processor 1. characteristics and specifications 1.1 ac and dc parametric specifications (agnd, dgnd=0 v, all voltages with respect to 0 v) 1.1.1 absolute maximum rating caution: operating beyond these minimum and maximum limits can result in perm anent dam- age to the device. cirrus logic recommends that cs98200 devices operate at the settings described in the next table. 1.1.2 recommended operating conditions 1.1.3 electrical characteristics symbol description min max unit vdd io power supply voltage on analog core and i/o ring -0,5 4.6 volts vdd core power supply voltage on core logic and pll -0.5 2.5 volts v i digital input applied voltage (power applied) -0.5 5.5 volts i i digital input forced current -10 10 ma i o digital output forced current -50 50 ma t sol lead soldering temperature - 260 o c t vsol vapor phase soldering temperature - 235 o c t stor storage temperature (no power applied) -40 125 o c t amb ambient temperature (power applied) 0 70 o c p total total power consumption - 2.2 w parameter symbol min typ max units supply voltage, analog and io v io & v aa 3.0 3.3 3.6 volts supply voltage, core logic and pll v pll & v dd 1.62 1.8 1.98 volts ambient temperature (power applied) t amb 02570 o c parameter symbol conditions min typ max units supply current, io i dd normal operating 65 ma supply current, core logic and pll i dd normal operating 210 ma input voltage, high v ih 2.0 - volts input voltage, low v il --0.8volts input current i in v in = v dd or v ss -1 - 1 a input pull up/down resistor r i -75- k ? output voltage, high v oh @ buffer rating 2.2 - - volts output voltage, low v ol @ buffer rating - - 0.4 volts high-z-state leakage i oz v out = v ss or v dd -1 - 1 a video dacs 1 r set = 174 ? dac resolution 10 bits dac to dac matching 2 mat 2 % output voltage range v out r load = 37.5 ? 3 1.28 volts
ds581pp2 ? copyright 2002 cirrus logic (all rights reserved) 9 cs98200 next generation dvd processor differential gain dg 1 % differential phase dp 0.5 % signal to noise snr 74 db chrominance am noise am 80 db chrominance pm noise pm 75 db 1. video parameters guaranteed only with 1% tolerance resistors or better for rset and rload. 2. only applies to each set of three dacs. 3. rload is a double terminated load, which includes a 75 ? resistor at the video dac and a 75 ? resistor at the video monitor.
10 ? copyright 2002 cirrus logic (all rights reserved) ds581pp2 cs98200 next generation dvd processor 2. timings 2.1 timing diagram conventions this data sheet contains timing diagrams. the following key explains the components used in these diagrams. any variations are clearly labeled when they occur. therefore, no additional meaning should be attached unless specifically stated. clock h igh to low h igh/low to h igh bus c hange bus valid u ndefined/invalid v a lid b u s to t ris ta te bus/signal o m ission figure 1. legend for timing diagrams
ds581pp2 ? copyright 2002 cirrus logic (all rights reserved) 11 cs98200 next generation dvd processor 2.2 dc characteristics ( t a = 25 c; v pll =v dd =1.8v10%, v io =v aa =3.3 v10%) 2.2.1 atapi interface cs98200 can interface with a atapi-type slave loader gluelessly. figure 2 illustrates a read atapi transaction and a write atapi transaction. symbol description min typ max unit t acyc 1 1. values are guaranteed by design only cycle time 87 ns t aavr address valid to hmrd-/hmwr- setup 7 ns t ah address hold from hmrd-/hmwr setup 11 ns t arww h_rd/h_wr pulse width 63 ns t arec h_rd/h_wr recovery time 21 ns t awsu h_wr data setup 30 ns t awh h_wr data hold 8 ns t ardsu h_rd data setup 20 ns t arddh h_rd data hold 0 ns t ardts h_rd data high-z-state 8 ns t arsu h_rdy setup time 14 ns t arh 1 h_rdy hold time 0 ns table 1. atapi interface characteristics h_a[2:0] , h_cs[3:0] h_d[15:0](write) h_d[15:0](read) h_rd/h_wr t acyc t aavr t arww t ah t arec t arsu t awh t awsu t ardsu t arddh t ardts t arh h_rdy(deasserted before tarsu) h_rdy(asserted before tarsu) figure 2. atapi interface timing diagram
12 ? copyright 2002 cirrus logic (all rights reserved) ds581pp2 cs98200 next generation dvd processor 2.2.2 dvd loader interface symbol description min typ max unit t dlckper dvdl_ck period 400 ns t dldisu dvdl_di setup time 5 ns t dldih dvdl_di hold time 10 ns t dldod dvdl_do output delay from falling edge 5ns t dlstbwd dvd_stb width 250 ns t dlstbl dvd_stb low time 40 % t dlstbh dvd_stb high time 40 % t dlreqod dvd_rdy output delay 90 ns t dlensu dvd_ena setup time 5 ns t dlenh dvd_ena hold time 5 ns t dldsu dvd_d[7:0] setup time 5 ns t dldh dvd_d[7:0] hold time 5 ns t dlsossu dvd_sos setup time 5 ns t dlsosh dvd_sos hold time 5 ns t lrcksu cd_lrck setup time 5 ns t cddsu cd_data setup time 5 ns t cddh cd_data hold time 5 ns t cdcpsu cd_c2po setup time 5 ns t cdcph cd_c2po hold time 5 ns figure 3. dvd loader host interface dvdl-ck (output) dvdl_rdy (input) dvdl_di (input) dvdl_do (output) d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 t dlckper t dldisu t dldih t dldod
ds581pp2 ? copyright 2002 cirrus logic (all rights reserved) 13 cs98200 next generation dvd processor figure 4. dvd loader data interface dvd_req (output) dvd_stb (input) dvd_ena (input) dvd_d[7:0] (input) dvd_sos (input) dvd_err (input) t dlstbwd t dlstbl t dlstbh t dlreqod t dlensu t dlenh t dldsu t dldh t dlsossu t dlsosh figure 5. dvd loader cd interface cd_bclk(input) cd_data (input) cd_lrck(input) cd_c2po (input) t lrcksu t cddsu t cddh t c2poh t c2posu
14 ? copyright 2002 cirrus logic (all rights reserved) ds581pp2 cs98200 next generation dvd processor figure 6. dvd loader cd interface for mats 15 0 1 cd_bck cd_lrck data c2p0 14 13 12 11 10 9 8 7 6 5 4 3 2 invalid 0 15 0 1 14 13 12 11 10 9 8 7 6 5 4 3 2 in va lid msblsb msblsb lower (left channel) upper (left channel) lower (right channel) upper (right channel) 32-bit bck, msb first, right channel low, c2p0 lsb first, data latch timing high 15 0 1 cd_bck cd_lrck data c2p0 14 13 12 11 10 9 8 7 6 5 4 3 2 invalid 0 15 0 1 14 13 12 11 10 9 8 7 6 5 4 3 2 in va lid msblsb msblsb upper (right channel) lower (right channel) upper (left channel) lower (left channel) 32-bit bck, msb first, left channel low, c2p0 msb first, data latch timing low 15 0 1 cd_bck cd_lrck data c2p0 141312111098765432 invalid 0 msb lsb lower (left channel) upper (left channel) lower (right channel) upper (right channel) 24-bit bck, msb first, right channel low, c2p0 msb first, data latch timing high left channel right channel right channel left channel left channel right channel 15 0 1 141312111098765432 in va lid msb lsb 15 14 13 12 11 10 9 8 7 6 5 invalid msb upper (left channel) left channel cd_bck cd_lrck data c2p0 invalid 0 lsb msb lower (left channel) upper (left channel) lower (right channel) upper (right channel) 24-bit bck, lsb first, right channel low, c2p0 msb first, data latch timing low left channel right channel in va lid lsb msb invalid lsb upper (left channel) left channel 015 114 13 12 11 10 9 8 7 6 5 4 3 2015 114 13 12 11 10 9 8 7 6 5 4 3 2 01 10 9 8 7 6 5 4 3 2 15 0 1 cd_bck cd_lrck data 141312111098765432 invalid 0 msb lsb 24-bit bck, msb first, right channel low, data latch timing high (note: no c2p0 for this format) left channel right channel 15 0 1 141312111098765432 in va lid msb lsb 15 14 13 12 11 10 9 8 7 6 5 invalid msb left channel 15 0 1 cd_bck cd_lrck data c2p0 141312111098765432 0 msb lsb lower (left channel) upper (left channel) lower (right channel) upper (right channel) 16-bit bck, msb first, left channel low, c2p0 lsb first, data latch timing high left ch annel right channel 15 0 1 14 13 12 11 10 9 8 7 6 5 4 3 2 msb lsb 15 0 1 141312111098765432 msb lsb lower (left channel) upper (left channel) lower (right channel) upper (right channel) left ch annel right channel 15 0 1 14 13 12 11 10 9 8 7 6 5 4 3 2 msb lsb 15 14 13 msb
ds581pp2 ? copyright 2002 cirrus logic (all rights reserved) 15 cs98200 next generation dvd processor 2.2.3 dvd serial interface timing symbol description min typ max unit tdsckper 1 dvds_clk period 33 ns tdsckl 1 dvds_clk low time 40 50 % tdsckh 1 dvds_clk high time 40 50 % tdsdsu dvds_data setup to dvds_clk active edge 5 ns tdsdhd dvds_data hold after dvds_clk active edge 5 ns tdscdsu dvds_vld, dvds_sos setup to dvds_clk 5 ns tdscdhd dvds_vld, dvds_sos hold after dvds_clk 5 ns 1. values are guaranteed by design only figure 7. dvd serial interface timing dvds_clk (input) dvds_data (input) dvds_vld, dvds_sos (input) dsckl dsckh dsdhd dscdhd dsckper t t t t dsdsu t dscdsu t t
16 ? copyright 2002 cirrus logic (all rights reserved) ds581pp2 cs98200 next generation dvd processor 2.2.4 sdram interface cs98200 interfaces with either sdram or sgram for high data bandwidth transfer. figure 8 shows the refresh cycle performed by cs98200. symbol description min typ max unit t mco output delay from m_cko active edge 9 ns t mper m_cko period 8 ns t mdow m_d[31:0] delay from m_cko 9 ns t msur m_d[31:0] setup to m_cko 3 ns t mhr m_d[31:0] hold time after m_cko 2.5 ns table 2. sdram interface characteristics m_cko m_a[10:0] m_bs0_n, m_ras_n m_cas_n m_we_n m_d[31:0] m_dqm_[3:0] m_ap m_bs1_n figure 8. sdram refresh transaction d0 d1 d2 d3 d4 d5 d6 d7 c1 c2 c3 c4 c5 c6 c7 c0 r0 m_cko m_a_[10:0] m_cke m_ras_n m_cas_n m_we_n m_d[31:0] m_dqm[3:0] 0 f f figure 9. sdram burst write transaction
ds581pp2 ? copyright 2002 cirrus logic (all rights reserved) 17 cs98200 next generation dvd processor d0 d1 d2 d3 d4 d5 d6 d7 c1 c2 c3 c4 c5 c6 c7 c0 r0 m_cko m_a_[10:0] m_cke m_ras_n m_cas_n m_we_n m_d[31:0] m_dqm[3:0] 0 f f figure 10. sdram burst read transaction m_ras_n,m_cas_n m_we_n,m_ap,m_dqm[3:0], m_cke,m_a[10:0] t mper t mco m_d[31:0](write) m_d[31:0](read) m_cko t msur t mhr t mdow figure 11. sdram timing
18 ? copyright 2002 cirrus logic (all rights reserved) ds581pp2 cs98200 next generation dvd processor 2.2.5 rom/nvram interface symbol description min typ max unit t rc read cycle time 75 ns t cds ce to data setup 80 ns t ods oe to data setup 70 ns t ads address to data setup 80 ns t aws address to we setup (write) 64 ns t cws ce to we setup (write) 64 ns t wp we pulse width (write) 160 ns t cdo ce to data output (write) 0 ns t dh we to data hold (write) 10 ns table 3. ram/nvrom characteristics figure 12. rom/nvram r eading timing nv_ce_n nv_we_n nv_oe_n (m_ap) address[22:0] m_d[7:0] t rc t ads t cds t ods
ds581pp2 ? copyright 2002 cirrus logic (all rights reserved) 19 cs98200 next generation dvd processor nv_ce_n nv_we_n nv_oe_n (m_ap) addr[22:0] m_d[7:0] t aws t cws t wdh t wp t cdo figure 13. rom/nvram write timing
20 ? copyright 2002 cirrus logic (all rights reserved) ds581pp2 cs98200 next generation dvd processor 2.2.6 digital video output interface figure 14 illustrates the signal timing for the digital video interface pins. symbol description min typ max unit t vocper 1 1. values are guaranteed by design only xtlclk period 37.037 ns t covo1 2 2. it is recommanded that the output data should be taken at the opposite edge of the clk27_o. vdat[7:0] delay from xtlclk -10 10 ns t covo2 2 vsync/hsync delay from xtlclk -10 10 ns table 4. cs98200 digital video interface char acteristics vout_clk (output) vout_d7:0] (output) vout_hs/vout_vs (output) t vocper t covo1 t covo2 figure 14. cs98200 digital video interface timing diagram
ds581pp2 ? copyright 2002 cirrus logic (all rights reserved) 21 cs98200 next generation dvd processor 2.2.7 video input interface . symbol description min typ max unit t vicper video clock input period 37.037 ns t sutc1 vin_d[7:0] setup time 5 ns t hvi vin_d[7:0] hold time 5 ns t sutc2 vin_hs/vs setup time 5 ns table 5. video input interface symbols and characterization data vin_clk vin_d[7-0] t sutc1 t hvi t vicper vin_hs,vin_vs t sutc2 figure 15. video input timing
22 ? copyright 2002 cirrus logic (all rights reserved) ds581pp2 cs98200 next generation dvd processor 2.2.8 audio input interface timing symbol description min typ max units t aicl audi_bck low time 1, 2 1. values are guaranteed by design only 2. active clock edge is programmable. timing is referenced from active edge 40 50 % t aich audi_bck high time 1, 2 40 50 % t aiper audi_bck period 1, 2 80 ns t lrts audi_lr setup time 5 - ns t sdsus audi_d setup time 5 - ns t sdhs audi_d hold time 5 - ns table 6. audio input interface symbols and characterization data figure 16. audio input timings audi_bck (input) audi_data (input) audi_lrck (input) t lrts t sdsus t sdhs t aich t aicl t aiper
ds581pp2 ? copyright 2002 cirrus logic (all rights reserved) 23 cs98200 next generation dvd processor 2.2.9 audio output interface timing figure 17 and figure 16 illustrate the signal timing for the digital audio pins. symbol description min typ max unit t axper aud_xclk period (input/output) 1, 2 13 - ns t axch aud_xclk high time (input/output) 1, 2 1. values are guaranteed by design only 2. active clock edge is programmable. timing is referenced from active edge 40 50 % t axcl aud_xclk low time (input/output) 1, 2 47 50 % t sdmo audo_bck delay from aud_xclk output rise 10 t sdmi audo_bck delay from aud_xclk input rise 20 t aoper audo_bck period (output) 1, 2 104 t lrds audo_lr delay from audo_bck output rise -10 10 ns t adsm audo_d[3:0] delay from audo_bck output rise -10 10 ns table 7. digital audio out characteristics figure 17. digital audio out timing diagram audo_bck(output) aud_xclk(input/output) t sdm t axch audo_bck(output) audo_do[3:0] (output) audo_lr(output) t lrds t adsm t axcl t axper t aoperl
24 ? copyright 2002 cirrus logic (all rights reserved) ds581pp2 cs98200 next generation dvd processor 2.2.10 miscellaneous timings symbol description min typ max unit t xccper 1 1. xtlclk must meet the requirement of external the video encoder for correct chroma (27 mhz 1 khz). xtlclk period 37.037 ns t rstl rst_n low pulse width 1000 ns t gph gpio pw high 50 ns t gpl gpio pw low 50 ns table 8. miscellaneous timing characteristics reset-n t gph t gpl t rstl xtlclock gpio xccper t figure 18. miscellaneous timings
ds581pp2 ? copyright 2002 cirrus logic (all rights reserved) 25 cs98200 next generation dvd processor 3. typical application the figure 19 shows a typical example of a complete dvd receiver solution using the cs98200. flash 2m (up to 8 mb) sdram 8m (up to 3 2 mb) .. . . digital interface receiver ir (4)audio dacs power reg. audio adc video decoder front panel cs98200 s/pdif input audio-l(4) audio-r(4) s-video composite video switch power cd loader (atapi, a/v) audio-l audio-r video component video 6 video dacs audio up to 8 channels s/pdif output remote keyboard control figure 19. cs98200 typical application
26 ? copyright 2002 cirrus logic (all rights reserved) ds581pp2 cs98200 next generation dvd processor 4. cs98200 device summary 4.1 block diagram the cs98200 block diagram is shown in figure 20 . 4.2 cs98200 device details 4.2.1 risc-32 processors two powerful 32-bit risc processors (risc0 and risc1), generation iii virtual memory support optimizing c compiler big or little endian data formats su pport mac multiply/accumulate in 2 cycles with c support 4 kbyte instruction cache, 2 kbyte data cache single cycle instructions, runs at 180 mhz 4.2.2 powerful 24/32-bit dsp powerful 24/32-bit dsp processor 24-bit fixed point logic, with 54-bit accumu- lator single-cycle throughput, 2-cycle latency multiply accumulate, 32-bit simple integer logic. 8-kbyte instruction cache single cycle instructions, runs at 180 mhz expanded 4 kbyte x + 16 kbyte y paged program visible local memory, total data ram = 20 kbytes 4.2.3 system controls includes several hardware lockable sema- phore registers general-purpose register for inter-processor communication 32-bit timers for i/o and other uses, with programmable interval rates both hardware and software interrupts on data or debug built in plls generate all required clocks from 27 mhz input clock 4.2.4 memory controller supports standard sdram and sgram, 32-bit data mode only, from 4 mbyte to 32 mbyte includes a separate dedicated dram clock, so memory can run asynchronous to the sys- tem clock pll ( main, audio, sdram) mpeg2 video decoder 2/4/8/16 bit osd t video processor (i/o, scale, pip, mix) subpic ture decoder risc1 (appl ication) pcm, spdif inter face audio ds p dma con trol (bitblt, css) mem control (sdram,rom) host interface (atapi,av,isa) external io (gpio, ir ) registers data addr graphics risc0 (navigation and control ) figure 20. cs98200 block diagram
ds581pp2 ? copyright 2002 cirrus logic (all rights reserved) 27 cs98200 next generation dvd processor high speed, can handle up to 120 mhz dram speeds supports 8-bit parallel rom or flash, up to 8 mb single bank of sdram only. single bank of rom/flash only separate data bus for rom, reduces loading for improved speed, also handles 5 v easier. 4.2.5 data flow engine 2432 bytes of internal memory dma to/from main ram into local sram supports endian conversion and byte, short, long data formats on dma supports block transfers for graphics bit blits 4.2.6 mpeg video decoder supports vcd, vcd 2.0, dvd video stan- dards supports trick features, including smooth 2x play and reverse play special anti-tearing logic controls picture de- code and presentation advanced error concealment hardware new acceleration modules for mpeg-4 sim- ple profiles support 4.2.7 system synchronization system time clock (stc) for audio/video synchronization flexible interrupt structure for controlling decode and presentation times hardware scheduling of subpicture and highlight events 4.2.8 audio interface supports 8 channels pcm output at up to 24 bits and 192 khz output rate. supports 2 channels i 2 s input at up to 24 bits and 96 khz input rate. simultaneous iec-958 (spdif) output with programmable channel status and user data. spdif, pcm input, and pcm output can all have different xclk dividers. supports simultaneous 192 khz front and 96 khz surround, for dvd audio 4.2.9 video input ntsc/pal video decoder input interface video input image can be displayed in small window, or as main picture 4.2.10 external interface serial i 2 c ? master and slave port 29 independent fully programmable bi-di- rectional i/o pins 8 edge or level detection interrupt pins hardware assisted support for infrared re- mote devices, such as remote control, infra- red keyboard dual uart 4.2.11 video processor supports 24-bit 4:2:0 and 4:2:2 video modes and 16-bit true color graphics modes. picture-in-picture module includes horizon- tal and vertical downscaling with program- mable output sizes, positions, and borders overlay mixer with rgb to yuv conversion and output formatting supports 4:2:0, 4:2:2, yuv655, rgb565 and rgb555 frame buffer inputs outputs 4:2:2 video in ccir-601 or ccir- 656 format high quality scaling using a vertical and a horizontal 16 taps polyphase programmable filter and supports any size image up to 768x576 3 taps adaptative anti-flicker filtering master or slave video sync configuration multiple video plains overlay (main video / video input / picture_in_picture / pic- ture/on-screen / display) gamma correction 4.2.12 sub-picture processor run-length decode dvd sub-pictures hardware vertical scaling supports ntsc- pal format conversion 16-level alpha blending 4.2.13 graphics engine 16 bit true color progressive and interlaced mode support
28 ? copyright 2002 cirrus logic (all rights reserved) ds581pp2 cs98200 next generation dvd processor supports gamma correction color-key type transparency support global blending support frame buffer wrap around support for scrolling 3 tap horizontal and vertical filtering 4.2.14 on screen display module supports 2-bit and 4-bit pixel modes 3 separate regions support 16 transparency overlay levels support 4.2.15 dvd loader interface 4-pin serial interface to low-cost dvd load- ers loader control via separate 2-wire serial master control port io channel interface supports standard 8 bit dvd loader protocols 4.2.16 cpu interface and sram controller internal sram of 32 kbyte, and controller, synchronous with the cpus at 180 mhz fast interfaces to riscs and dsp asynchronous interfaces to the main system clock special dma engine, with multiple software clients, and command fifo special interface to mpeg-4 video module 4.2.17 host bus interface programmable parallel host master interface supports formats including atapi, isa, and more internal dma module, for i/o type reads and writes on the host bus extra chip selects, for more external devices 4.2.18 video encoder six 10-bit video dacs, drive 37.5 w load di- rectly without external buffering supports pal (b, d, g, h, i, n, m, 60) and ntsc component (rbg or yuv) or composite + s- video output progressive or interlaced mode output macrovision 7.1 support (interlaced) and macrovision 1.03 support (progressive) wide-screen signalling support (interlaced and progressive) and cgms support closed captioning support 4.2.19 system functions 240-pin mqfp package all i/o pins are 3 v with 5v tolerance advanced 0.18 micron cmos technology internal processors run at 180 mhz supports low power modes and clock shut- off
ds581pp2 ? copyright 2002 cirrus logic (all rights reserved) 29 cs98200 next generation dvd processor 5. functional description 5.1 risc processor the cs98200 includes two powerful, third-gen- eration proprietary 32-bit risc processors, risc0 and risc1, with optimizing c compiler support and source level debugger. the risc processors fully support many real time oper- ation systems (rtos). the dvd application user interface resides on risc1 and is customer programmable. the real time control of low lev- el dvd functions is performed by risc0. risc1 gains access to system resources controlled by risc0 via calls through an applications pro- gramming interface, see the cs98200 software api . all risc0 firmware, api and sample appli- cation code are supplied with the cs98200. the risc processors also have a mac engine, which performs multiply/accumulate in 2 cy- cles in a pipelined fashion with c support, effec- tively achieving single cycle throughout. the risc0 processor coordinates on-chip multi- threaded tasks, as well as system activities such as remote control and front panel control. the dvd application end-user interface resides on risc1, and any modifications to that interface occur through the cs98200 api. 5.2 dsp processor the cs98200 contains a proprietary digital sig- nal processor (dsp), which is optimized for au- dio applications. the dsp performs 32-bit simple integer operations, and has a 24-bit fixed point logic unit, with a 54-bit accumulator. the multiply-accumulator has single-cycle through- put, with two cycle latency. the dsp is opti- mized for bit packing and unpacking operations. the interface to main memory is de- signed for handling flexible block sizes and skip counts. 5.3 memory control the dram interface performs the sdram con- trol and arbitration functions for all the other modules in the cs98200. the dram interface services and arbitrates a number of clients and stores their code and/or data within the local memory. this arbitration and scheduling guar- antees the allocation of sufficient bandwidth to the various clients. the dram interface sup- ports up to 32 mbytes. for a typical dvd player application, cs98200 requires 8 mbytes memo- ry space. sharing the same interface, cs98200 also sup- ports flash rom, otp, or mask rom inter- face. code is stored in rom. after the system is booted, the code is shadowed inside sdram for execution. the flash rom interface is pro- vided so that the code can be upgraded in the field once the communications channel is estab- lished. utility software will be provided to de- bug and upgrade code for the system manufacturer. 5.4 dataflow control (dma) the dma controller moves data between the external memory and internal memory. the ex- ternal memory address can be specified using a register, or in fifo mode, using start and end address registers. separate start/end address registers are used for dma read and write oper- ations. the dma interface also has a block transfer function, which allows for the transfer of one block of data from one external memory location to another external memory location. in effect, this feature combines a dma read and write into one operation. in addition, the dma write operation allows for byte, short, word, and other types of masking. 5.5 system control functions the system control functions are used to coordi- nate the activities of the multiple processors, and to provide the supporting system opera- tions. eight 32-bit communication registers are available for inter-processor communication, and 32 semaphore registers are used for re- source locking. timers are available for general- purpose functions, as well as more specialized
30 ? copyright 2002 cirrus logic (all rights reserved) ds581pp2 cs98200 next generation dvd processor functions such as watchdog timers and perfor- mance monitoring. the large number of general purpose i/os of- fers flexibility in system configurations. an i 2 c master allows for control of other i 2 c devices, such as a video encoder. an i 2 c slave port shares the same pins, and can be used for debug functions. interrupts can be generated on specif- ic or generic events. infrared inputs can be fil- tered to make them free of glitches or stored unfiltered into memory. control of all the inter- nal clocks is also possible. there are two sepa- rate plls that are clocked by the 27 mhz clock input. one pll generates the main clock and dram interface clock, and the second gener- ates the audio 256x/384x clock. 5.6 dvd/atapi interface the cs98200 has a programmable interface port which can be configured to connect to industry standard cd/dvd loaders without external glue logic. the cd/dvd interface fully sup- ports many popular cd/dvd loaders. the in- terface consists of dvd control and data ports and an optional cd control/data port. the cs98200 hardware manages the dvd inter- face and moving data to an arbitrary size input fifo in dram. the same interface pins can be optionally configured as a generic 16-bit host master port. in this mode, the cs98200 can con- trol up to four devices (using 4 chip select out- puts), each of which may use different protocol and timing. the interface can be set up in ata- pi mode, to connect directly to any atapi dvd loader (using two chip selects). si- multaneously, the other two chip selects can be configured to connect to other devices, such as a super i/o chip or hard disk. a third option is to configure the interface for micro-less dvd loader operation, which may also be configured to connect without external glue logic. 5.7 serial dvd interface the cs98200 has a 4-pin serial port which inter- faces to the data port of popular low-cost dvd loaders. this type of loader provides for low system cost by eliminating the track buffer, in- terface fifo, and flow control logic. the cs98200 contains a large internal sram to han- dle high burst data rates, without requiring re- verse flow control. the cs98200 performs error detection, sector number tracking, and interrupt generation. 5.8 mpeg video decoding compressed mpeg data is read from the dvd disk into an input fifo in dram. the data flow (dma) controller moves video packets from the input fifo into the mpeg decoder ? s input fifo (also in dram). the dma controller can also perform advanced functions such as start code search, relieving the risc processors. the sys- tem synchronization function is used to control the timing of mpeg picture decoding. the mpeg video decoder processes i, b, and p frames, and writes to video frame buffers in dram for output to the display. special anti- tearing logic ensures that currently displayed frame buffers are not overwritten. 5.9 audio processing compressed audio data is read from the dvd disk into an input fifo in dram. the data is decompressed, then written to a pcm output fifo, also in dram. presentation time stamps (pts) are extracted from the stream to update the stc, in order to maintain audio/video syn- chronization. the dma and decompression stages of audio processing can be done with a combination of the dma unit, dsp, and risc processors. the dsp is optimized for audio processing, so most common formats can be handled by the dsp alone, including ac-3, dts, mpeg2 audio, and mp3. the dsp has enough reserve bandwidth
ds581pp2 ? copyright 2002 cirrus logic (all rights reserved) 31 cs98200 next generation dvd processor to handle the karaoke echo-mix and pitch shift, and ac-3 down-mix functions. the audio output data is written into a dram fifo in 16-, 18-, 20- or 24-bit pcm format. a flexible audio output stage can simultaneously output 8 channels of pcm data to audio dacs up to 192 khz sample rate, plus an iec-958 en- coded output at up to 48 khz. the audio inter- face also includes a flexible audio input interface, which can input a wide range of pro- tocols from an audio adc or an iec-958 receiv- er at up to 96 khz.
32 ? copyright 2002 cirrus logic (all rights reserved) ds581pp2 cs98200 next generation dvd processor 5.10 video encoder with progressive video dacs the cs98200 incorporates an enhanced video encoder with six 10-bit video dacs that drive double terminated 75 ? directly without exter- nal buffering. these termination resistors should be located as close as possible to the cs98200. all analog video outputs should be connected through filters to video connectors (tv/monitor). the video filters should be locat- ed as close as possible to the video connectors. two schottky diodes should be connected to each output in order to protect the cs98200 from surges caused by being connected and dis- connected to the external devices. figure 21 shows the video dac connections. six 10-bit dacs provide two channels for an s- video output port, one composite video output, and three rgb or y, pb, pr outputs. video out- put can be formatted to be compatible with ntsc (m,j), pal (b, d, g, h, i, m, 60), and 480p. the video encoder is compliant with both mac- rovision 7.1 for the interlaced video (ntsc, pal) and 1.03 for the progressive scan (480p). the video encoder also supports wss (wide- screen signaling), cgms (copy generation management system), and closed caption. cs98200 comp 1&2 rset 1&2 vref 1&2 y c cv yg vr ub 3.3v 174 ? 1% 0.01uf 0.01uf yout vidoe filter video filter video filter video filter video filter video filter c out cv out vr out yg out ub out 75 ? 1% 270pf 330pf 1.8uh 22pf 10uf figure 21. video dac connections
ds581pp2 ? copyright 2002 cirrus logic (all rights reserved) 33 cs98200 next generation dvd processor 5.11 video input/output interface in addition to the six 10-bit video dacs, the cs98200 provides a separate digital video in- terface that will give you flexible and powerful means of outputting digital video data to exter- nal devices in ccir601/3 and ccir656 formats. the interface directly supports ntsc/pal vid- eo encoding, in both master and slave synchro- nization configurations. the internal frame buffer format could be 4:2:0, 4:2:2, yuv655, rgb565 and rgb555. the cs98200 also features an ntsc/pal video decoder input interface. the interface accepts ccir601, cif, and qcif formats, out of many tv decoders on the market. the video processor also allows overlay of multiple video planes (main video / video input / picture_in_picture / on-screen display). the video input scaler (vis) module inputs 8- bit digital video data from a camera or pal/ntsc decoder and simply dump all the data to dram. the scaled image, with a border, can be overlaid anywhere on the screen into a ? or ? -screen sized window by the picture in pic- ture (pip) module. an alternate method of using the video input function is to input a full sized picture and present it on the screen full size (bypass mode). in this mode, the pip module can place full mo- tion dvd images in the small window. an inter- nal glitch-free mux can switch the video processor clock source from the internal clock to the video input clock, allowing the pip mode to switch back and forth on the fly, with no drop- out.
34 ? copyright 2002 cirrus logic (all rights reserved) ds581pp2 cs98200 next generation dvd processor 5.12 universal asynchronous receiver/transmitters (uarts) the uart performs serial-to-parallel conver- sion on data characters received from a periph- eral device and parallel-to-serial conversion on data characters received from the host proces- sor. figure 22 shows rxd and txd data trans- fers over the uart interface. the cs98200 has 2 uart interfaces based on a ns16550-compatible design, which incorpo- rates 16-byte transmit and receive fifos to en- hance performance and throughput. as with the 16650, it can operate in both fifo-mode (16550) or in the original non-fifo mode (16450). the main registers are identical in structure to the ns16550, but some unused bits have been enabled for added functionality. the standard features are: compatible with 16450 uart 16-byte transmit and receive fifos reduce number of interrupts presented to cpu generates and detects standard asynchronous communication bits (start, stop and parity) to and from serial data independently controlled transmit, receive, line status and data set interrupts programmable baud rate generator (16 bit divisor) modem control interface (cts, rts, dsr, dtr, ri and dcd) fully programmable serial-interface characteristics: ? 5, 6, 7 or 8 bit characters ? even, odd or no-parity bit generation/detection ? 1, 1 ? , or 2 stop bit generation false start bit detection complete status reporting capabilities line break generation and detection internal loopback diagnostic mode programmable trigger levels for fifos selectable dma signaling mode prioritized interrupts transmitter and receiver fifo time-out interrupts additional optimizations: byte enable register allows transfer of up to 4 bytes in a single register write (only in fifo mode). external loopback diagnostic mode separate baud clock input available additional receiver error information note: if using separate baud clock, it must be less than ? frequency of the system clock, otherwise, you must use the system clock. rxd txd parity data bits (5~8) start stop parity data bits (5~8) start stop start figure 22. uart data transfer
ds581pp2 ? copyright 2002 cirrus logic (all rights reserved) 35 cs98200 next generation dvd processor 6. memory map 6.1 processor memory map the cs98200 externally supports up to 32 mbytes dram and 16 mbytes rom/nvram. tab le 9 , table 10, and tabl e 11 on the next page list the memory map as viewed by the risc processors, and identifies whether each segment is mapped or cacheable. for detailed information on programming cs98200 memory, see cs98200 memory interface user ? s manual (ds525umd1). address description cached 0x8000_0000 - 0x8000_7fff internal sram (32 kbytes) yes 0x8200_0000 - 0x83ff_ffff external dram (32 mbytes) yes 0x9400_0000 - 0x97ff_ffff external dram w/ dcache flush (32 mbytes) yes 0x9800_0000 - 0x9bff_ffff external rom/nvram read/write (16 mbytes) yes 0x9c00_0000 - 0x9fff_ffff external rom/nvram read only (16 mbytes) yes 0xa000_0000 - 0xa000_7fff internal sram (32 kbytes) no 0xa200_0000 - 0xa3ff_ffff external dram (32 mbytes) no 0xb000_0000 - 0xb003_ffff internal registers and srams no 0xb400_0000 - 0xb7ff_ffff external dram w/ dcache flush (32 mbytes) no 0xb800_0000 - 0xbbff_ffff external rom/nvram read/write (16 mbytes) no 0xbc00_0000 - 0xbfff_ffff external rom/nvram read only (16 mbytes) no table 9. memory map-risc0 processor host byte address description 0x0000_0000 - 0x0003_ffff internal registers and srams 0x1000_0000 - 0x11ff_ffff external dram (32 mbytes) 0x1200_0000 - 0x13ff_fff internal sram 0x1400_0000 - 0x14ff_ffff external rom/nvram space (16 mbytes) table 10. host debug port address map byte address offset description 0x0000_0000 - 0x0003_ffff (i/o space) internal registers and srams 0x0000_0000 - 0x01ff_ffff (memory space) external dram (32 mbytes) 0x0200_0000 - 0x0200_7fff (memory space) internal sram (32 kbytes) table 11. dsp address map
36 ? copyright 2002 cirrus logic (all rights reserved) ds581pp2 cs98200 next generation dvd processor 7. 240-pin mqfp pin description 7.1 240-pin mqfp pin layout figure 23 shows the layout of all the pins for the 240-pin mqfp package. the direction of the arrow by each pin shows whether the pin is an input, output, or bidirectional. cs98200 240-pin mqfp 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 51 50 52 1 ir_in cdc_clk cdc_sync cdc_sdo cdc_sdi m_d_29 io_g nd m_d_28 m_d_27 m_d_26 m_d_25 io_3v3 m_d_30 m_d_31 m_d_23 dig_1v8 dig_1v8 dig_gnd dig_gnd io_g nd m_d_21 m_d_20 m_d_19 m_d_18 m_d_17 io_3v3 io_3v3 io_g nd m_dqm_1 m_dqm_3 m_d_14 m_d_13 m_d_6 m_d_5 m_dqm_2 m_d_22 rst_n test pll_1v8 m_d_24 m_d_16 m_d_15 m_d_12 m_d_11 io_3v3 m_d_10 io_g nd m_d_9 m_d_8 io_g nd m_d_7 m_d_4 53 54 55 57 56 58 59 60 m_d_3 vin_d_1 vin_d_0 io_3v3 m_d_2 vin_d_3 m_d_1 vin_d_2 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 70 71 69 120 68 67 66 64 65 63 62 61 dvdl_di dvd_rdy pwm_o rxd_2 txd_2 sda1 scl1 vin_d_7 io_3v3 vin_d_6 vin_d_5 vin_d_4 scl2 sda2 dig_1v8 nv_d_6 io_3v3 m_a_9 io_gnd nv_d_5 nv_d_4 nv_d_3 nv_d_2 nv_d_1 nv_d_0 m_a_0 rxd_1 m_a_3 io_3v3 txd_1 io_gnd dig_gnd io_gnd m_cas_n m_a_2 dig_gnd dvdl_ck dvdl_do pll_1v8 nv_d_7 m_a_1 m_a_4 m_a_5 dig_1v8 m_a_6 m_a_7 m_a_8 m_a_10 nv_ce_n m_bs0_n m_we_n m_ras_n m_bs1_n io_gnd m_cko m_ap m_cke m_d_0 io_3v3 m_dqm_0 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 130 131 129 180 128 127 126 124 125 123 122 121 h_ale h_a_3 dvd_d_1 dvd_d_0 h_a_2 dvdl_rdy dac_a3v3 dac_a3v3 dac_agnd dac_a3v3 dac_agnd vref1 dig_1v8 h_a_0 comp1 dac_agnd h_d_7 h_d_9 cv_out dac_agnd dac_a3v3 y_out dac_agnd dac_a3v3 c_out dac_dgnd h_a_1 cd_c2p0 cd_data dig_gnd cd_bclk h_d_15 io_gnd vin_clk dac_agnd dac_a3v3 dvd_d_3 dvd_d_2 pll_1v8 iset1 dac_d1v8 cd_lrck h_d_14 h_d_13 h_d_12 h_d_11 h_d_10 h_d_8 h_d_6 vin_hs h_d_5 io_3v3 vin_vs h_d_0 h_d_1 h_d_4 h_d_3 pll_1v8 h_d_2 io_gnd 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 231 230 232 181 233 234 235 237 236 238 239 240 dvd_d_6 dvd_d_7 h_cs_0 h_cs_1 io_3v3 h_wr h_rdy spi_clk spi_do spi_di spi_rdy audi_d h_rd h_cs_3 audi_bck dac_agnd aud_xclk audo_bck dac_dgnd ub_out dac_a3v3 dac_agnd yg_out dac_a3v3 dac_agnd vr_out h_cs_2 comp2 is et2 io_gnd dac_agnd dac_a3v3 audo_d_3 io_3v3 dac_agnd dac_d1v8 dvd_d_4 dvd_d_5 pll_gnd audi_lr dac_a3v3 vref2 dac_agnd dac_a3v3 dac_a3v3 audo_lr dig_1v8 dig_gnd audo_d_1 xtlclk_o audo_d_2 xtlclk_i io_gnd dvd_sos dvd_ena audo_d_0 spdif_o pll_gnd dvd_stb dvd_err figure 23. 240-pin mqfp pin layout
ds581pp2 ? copyright 2002 cirrus logic (all rights reserved) 37 cs98200 next generation dvd processor 7.2 240-pin mqfp pin summary figure 24 shows the pin names associated with each type of cs98200 interface. 7.3 pin configuration summary the cs98200 has flexible pin functionality. tab l e 12 lists the different possible pin configurations and the settings required. the io_set value is programmed through a register, while the audo_d_0 and audo_lr values are set through pull up or pull down resistors on the pins. io_set[1:0] audo_d_0 audo_lr host/atapi pins video in/out pins dvd pins 00 1 x host master mode video in mode dvd mode 00 0 0 host slave mode video in mode dvd mode 00 0 1 host master mode video in mode host slave mode 01 1 x host master mode video out mode video in mode 01 0 0 host slave mode video out mode video in mode 01 0 1 host master mode video out mode host slave mode 10 1 x dvd mode video in mode gpio mode 10 0 0 host slave mode video in mode gpio mode 10 0 1 dvd mode video in mode host slave mode 11 1 x dvd mode video out mode video in mode 11 0 0 host slave mode video out mode video in mode 11 0 1 dvd mode video out mode host slave mode table 12. pin configuration summary figure 24. 240-pin mqfp pinout summary h_d_[15:0] h_cs_[3:0] h _ a _[3 :0] h_ale h_rd h_w r h_rdy dvd_d[7:0] dvdl_rdy dvd_stb dvd_ena m _a_[10:0] m_bs0_n m _d_[31:0] m_dqm_[3:0] m_ras_n m_cas_n m_ap m _cke m _cko m_we_n nv_ce_n vin_hs/vout_hs vin_vs/vout_vs vin_clk/vout_clk vin_d[7:0]/vout_d[7:0] audi_bck audi_lr audi_d_[3:0] audo_bck audo_lr au d o _d _[3:0] ir _in test xtlclo ck_i rst_n cs98200 h ost m aster/ atapi (28) memory in te rfa c e (64) video in/o ut (11) audio o ut (8 ) m isc. (5) audio input (5 ) spdif_o dvd loader interface (20) uarts (4) power/gnd: (68) m_bs1_n nv_d [7:0] aud_xclk rxd_1 txd_1 rxd_2 txd_2 i 2 c debug (4) scl1 sda1 scl2 sda2 xtlclo ck_o dvd_sos dvd_err dvd_rdy dvdl_di dvdl_do dvdl_ck cd_bclk cd_lrck cd_data cd_c2po
38 ? copyright 2002 cirrus logic (all rights reserved) ds581pp2 cs98200 next generation dvd processor 7.4 explanation of pin types tabl e 13 lists the conventions used to identify the pin type and direction. 7.5 240-pin mqfp pin assignments tabl e 14 lists the pin number, pin name, and pin type for the 240-pin cs98200 package. the primary function and pin direction is shown for all signal pins. for some signal pins, a secondary function (or functions) and direction are also shown. for pins having more than one function, the primary function is chosen when the c hip is reset. pin type direction i input is input, with schmitt trigger id input, with pull down resistor iu input, with pull up resistor o output o4 output ? 4 ma drive o8 output ? 8 ma drive t4 high-z output ? 4ma drive b bi-direction b4 bi-direction ? 4 ma drive b4u bi-direction ? 4 ma drive, with pull-up b8u bi-direction ? 8 ma drive, with pull-up b4s bi-direction ? 4 ma drive, with schmitt trigger b4su bi-direction ? 4 ma drive, with pull-up and schmitt trigger pwr +1.8 v or +3.3 v power supply voltage gnd power supply ground name_n low active table 13. pin type legen d pin # pin name type primary function dir secondary function(s) dir 1 pll_1v8 pwr pll power 1.8 v 2 rst_n isu reset i 3 test i manufacturing test i 4 ir_in isu ir in i 5 cdc_clk b4s gpio_mis[18] b 6 cdc_sync b4s gpio_mis[19] b 7 cdc_sdo b4s gpio_mis[20] b 8 cdc_sdi b4s gpio_mis[21] b 9 io_3v3 pwr io power 3.3 v 10 m_dqm_3 b8 dram byte_enable[3] o table 14. 240-pin mqfp pin assignments
ds581pp2 ? copyright 2002 cirrus logic (all rights reserved) 39 cs98200 next generation dvd processor 11 m_d_31 b8 dram data[31] b 12 m_d_30 b8 dram data[30] b 13 m_d_29 b8 dram data[29] b 14 io_gnd gnd io ground 15 m_d_28 b8 dram data[28] b nvram address[23] o 16 m_d_27 b8 dram data[27] b nvram address[22] o 17 m_d_26 b8 dram data[26] b nvram address[21] o 18 m_d_25 b8 dram data[25] b nvram address[20] o 19 io_3v3 pwr io power 3.3 v 20 m_d_24 b8 dram data[24] b nvram address[19] o 21 m_d_23 b8 dram data[23] b nvram address[18] o 22 dig_1v8 pwr digital power 1.8 v 23 m_d_22 b8 dram data[22] b nvram address[17] o 24 dig_gnd gnd digital ground 25 io_gnd gnd io ground 26 m_d_21 b8 dram data[21] b nvram address[16] o 27 m_d_20 b8 dram data[20] b nvram address[15] o 28 m_d_19 b8 dram data[19] b nvram address[14] o 29 m_d_18 b8 dram data[18] b nvram address[13] o 30 m_d_17 b8 dram data[17] b nvram address[12] o 31 io_3v3 pwr io power 3.3 v 32 m_d_16 b8 dram data[16] b nvram address[11] o 33 m_dqm_2 b8 dram byte_enable[2] o 34 io_gnd gnd io ground 35 m_dqm_1 b8 dram byte_enable[1] o 36 m_d_15 b8 dram data[15] b 37 m_d_14 b8 dram data[14] b 38 m_d_13 b8 dram data[13] b 39 m_d_12 b8 dram data[12] b 40 m_d_11 b8 dram data[11] b 41 io_3v3 pwr io power 3.3 v pin # pin name type primary function dir secondary function(s) dir table 14. 240-pin mqfp pin assignments (continued)
40 ? copyright 2002 cirrus logic (all rights reserved) ds581pp2 cs98200 next generation dvd processor 42 m_d_10 b8 dram data[10] b 43 io_gnd gnd io ground 44 dig_gnd gnd digital ground 45 m_d_9 b8 dram data[9] b 46 dig_1v8 pwr digital power 1.8 v 47 m_d_8 b8 dram data[8] b 48 m_d_7 b8 dram data[7] b 49 m_d_6 b8 dram data[6] b 50 m_d_5 b8 dram data[5] b 51 m_d_4 b8 dram data[4] b 52 io_gnd gnd io ground 53 m_d_3 b8 dram data[3] b 54 io_3v3 pwr io power 3.3 v 55 m_d_2 b8 dram data[2] b 56 m_d_1 b8 dram data[1] b 57 vin_d_0 b4 primary video_in data[0] i (1.) secondary video_out data[0] (2.) gpio_vis[0] o b 58 vin_d_1 b4 primary video_in data[1] i (1.) secondary video_out data[1] (2.) gpio_vis[1] o b 59 vin_d_2 b4 primary video_in data[2] i (1.) secondary video_out data[2] (2.) gpio_vis[2] o b 60 vin_d_3 b4 primary video_in data[3] i (1.) secondary video_out data[3] (2.) gpio_vis[3] o b 61 m_d_0 b8 dram data[0] b 62 m_dqm_0 b8 dram byte_en[0] o 63 io_gnd gnd io ground 64 m_cko o8 dram clock o drc_clock eternal input i 65 io_3v3 pwr io power 3.3 v 66 m_cke b8 dram clock enable o 67 m_ap b8 dram auto precharge o nvram_oe_n o 68 m_bs1_n b8 dram banksel[1] o 69 m_bs0_n b8 dram banksel[0] o 70 m_ras_n b8 dram row strobe o pin # pin name type primary function dir secondary function(s) dir table 14. 240-pin mqfp pin assignments (continued)
ds581pp2 ? copyright 2002 cirrus logic (all rights reserved) 41 cs98200 next generation dvd processor 71 m_cas_n b8 dram col. strobe o 72 io_gnd gnd io ground 73 m_we_n b8 dram write enable o nvram_we_n o 74 nv_ce_n o4 rom chip enable o 75 io_3v3 pwr io power 3.3 v 76 m_a_10 b8 dram address[10] o nvram address[10] o 77 m_a_9 b8 dram address[9] o nvram address[9] o 78 m_a_8 b8 dram address[8] o nvram address[8] o 79 m_a_7 b8 dram address[7] o nvram address[7] o 80 m_a_6 b8 dram address[6] o nvram address[6] o 81 dig_1v8 pwr digital power 1.8 v 82 m_a_5 b8 dram address[5] o nvram address[5] o 83 dig_gnd gnd digital ground 84 io_gnd gnd io ground 85 m_a_4 b8 dram address[4] o nvram address[4] o 86 io_3v3 pwr io power 3.3 v 87 m_a_3 b8 dram address[3] o nvram address[3] o 88 m_a_2 b8 dram address[2] o nvram address[2] o 89 m_a_1 b8 dram address[1] o nvram address[1] o 90 m_a_0 b8 dram address[0] o nvram address[0] o 91 nv_d_0 b8 nvram data[0] b 92 nv_d_1 b8 nvram data[1] b 93 nv_d_2 b8 nvram data[2] b 94 nv_d_3 b8 nvram data[3] b 95 nv_d_4 b8 nvram data[4] b 96 nv_d_5 b8 nvram data[5] b 97 io_gnd gnd io ground 98 dig_gnd gnd digital ground 99 nv_d_6 b8 nvram data[6] 100 dig_1v8 pwr digital power 1.8 v 101 nv_d_7 b8 nvram data[7] pin # pin name type primary function dir secondary function(s) dir table 14. 240-pin mqfp pin assignments (continued)
42 ? copyright 2002 cirrus logic (all rights reserved) ds581pp2 cs98200 next generation dvd processor 102 vin_d_4 b4 primary video_in data[4] i (1.) secondary video_out data[4] (2.) gpio_vis[4] o b 103 vin_d_5 b4 primary video_in data[5] i (1.) secondary video_out data[5] (2.) gpio_vis[5] o b 104 vin_d_6 b4 primary video_in data[6] i (1.) secondary video_out data[6] (2.) gpio_vis[6] o b 105 io_3v3 pwr io power 3.3 v 106 vin_d_7 b4 primary video_in data[7] i (1.) secondary video_out data[7] (2.) gpio_vis[7] o b 107 scl1 b4su i 2 c debug slave b 108 sda1 b4su i 2 c debug slave b 109 scl2 b4su i 2 c master/simple slave b gpio_mis[0] b 110 sda2 b4su i 2 c master/simple slave b gpio_mis[1] b 111 txd_1 b4 uart1 tx data o gpio_mis[6] b 112 rxd_1 b4 uart1 rx data i gpio_mis[7] b 113 txd_2 b4 uart2 tx data o gpio_mis[8] b 114 rxd_2 b4 uart2 rx data i gpio_mis[9] b 115 pwm_o b4 pwm output o gpio_mis[10] b 116 dvd_rdy b4 prim. dvd loader data request o gpio_dvd[12] b 117 dvdl_di b4 primary dvd control data in i (1.) secondary video_in vsync (2.) gpio_dvd[13] (3.) secondary host slave read i b i 118 dvdl_do b4 primary dvd control data out o (1.) secondary video_in hsync (2.) gpio_dvd[14] (3.) secondary host slave write i b i 119 dvdl_ck b4s primary dvd control clock o (1.) secondary video_in clock (2.) gpio_dvd[15] (3.) secondary host slave ready i b o 120 pll_1v8 pwr pll power 1.8 v 121 pll_gnd gnd pll ground 122 io_gnd gnd io ground 123 h_d_0 b4 host master data[0] b (1.) secondary dvd data[0] (2.) gpio_hst[0] (3.) primary host slave data[0] (4.) primary video_out data[0] i b b o pin # pin name type primary function dir secondary function(s) dir table 14. 240-pin mqfp pin assignments (continued)
ds581pp2 ? copyright 2002 cirrus logic (all rights reserved) 43 cs98200 next generation dvd processor 124 h_d_1 b4 host master data[1] b (1.) secondary dvd data[1] (2.) gpio_hst[1] (3.) primary host slave data[1] (4.) primary video_out data[1] i b b o 125 h_d_2 b4 host master data[2] b (1.) secondary dvd data[2] (2.) gpio_hst[2] (3.) primary host slave data[2] (4.) primary video_out data[2] i b b o 126 h_d_3 b4 host master data[3] b (1.) secondary dvd data[3] (2.) gpio_hst[3] (3.) primary host slave data[3] (4.) primary video_out data[3] i b b o 127 h_d_4 b4 host master data[4] b (1.) secondary dvd data[4] (2.) gpio_hst[4] (3.) primary host slave data[4] (4.) primary video_out data[4] i b b o 128 vin_vs b4 primary video_in vsync i (1.) secondary video_out vsync (2.) gpio_vis[8] (3.) host master chip select[4] o b o 129 vin_hs b4 primary video_in hsync i (1.) secondary video_out hsync (2.) gpio_vis[9] (3.) host master chip select[5] o b o 130 io_3v3 pwr io power 3.3 v 131 vin_clk b4s primary video_in clock i (1.) secondary video_out clock (2.) gpio_vis[10] o b 132 io_gnd gnd io ground 133 h_d_5 b4 host master data[5] b (1.) secondary dvd data[5] (2.) gpio_hst[5] (3.) primary host slave data[5] (4.) primary video_out data[5] i b b o 134 h_d_6 b4 host master data[6] b (1.) secondary dvd data[6] (2.) gpio_hst[6] (3.) primary host slave data[6] (4.) primary video_out data[6] i b b o 135 h_d_7 b4 host master data[7] b (1.) secondary dvd data[7] (2.) gpio_hst[7] (3.) primary host slave data[7] (4.) primary video_out data[7] i b b o 136 h_d_8 b4 host master data[8] b (1.) secondary dvd control clock (2.) gpio_hst[8] o b 137 h_d_9 b4 host master data[9] b (1.) secondary dvd control ready (2.) gpio_hst[9] i b 138 h_d_10 b4 host master data[10] b (1.) secondary dvd control data out (2.) gpio_hst[10] o b 139 h_d_11 b4 host master data[11] b (1.) secondary dvd control data in (2.) gpio_hst[11] i b pin # pin name type primary function dir secondary function(s) dir table 14. 240-pin mqfp pin assignments (continued)
44 ? copyright 2002 cirrus logic (all rights reserved) ds581pp2 cs98200 next generation dvd processor 140 h_d_12 b4 host master data[12] b (1.) secondary cd c2p0 (2.) gpio_hst[12] (3.) secondary dvds_vld i b i 141 h_d_13 b4s host master data[13] b (1.) secondary cd_bclk (2.) gpio_hst[13] (3.) secondary dvds_clk i b i 142 h_d_14 b4 host master data[14] b (1.) secondary cd_lrlk (2.) gpio_hst[14] (3.) secondary dvds_sos i b i 143 h_d_15 b4 host master data[15] b (1.) secondary cd_data (2.) gpio_hst[15] (3.) secondary dvds_data i b i 144 cd_bclk b4s primary cd bit clock i (1.) primary dvds_clk (2.) gpio_dvd[17] (3.) secondary host slave address[0] i b i 145 cd_lrck b4 primary cd l/r clock i (1.) primary dvds_sos (2.) gpio_dvd[18] (3.) secondary host slave address[1] i b i 146 cd_data b4 primary cd data i (1.) primary dvds_data (2.) gpio_dvd[19] (3.) secondary host slave address[2] i b i 147 cd_c2p0 b4 primary cd c2p0 i (1.) primary dvds_vld (2.) gpio_dvd[20] (3.) secondary host slave address[3] i b b 148 dac_agnd gnd analog ground 149 dac_d1v8 pwr digital power 1.8 v 150 dac_dgnd gnd digital ground 151 c_out anlg c_out 152 dac_a3v3 pwr analog power 3.3 v 153 dac_agnd gnd analog ground 154 y_out anlg y_out 155 dac_a3v3 pwr analog power 3.3 v 156 dac_agnd gnd analog ground 157 cv_out anlg cv_out 158 dac_a3v3 pwr analog power 3.3 v 159 dac_agnd gnd analog ground 160 comp1 anlg compensation 161 iset1 anlg current set 162 vref1 anlg voltage ref pin # pin name type primary function dir secondary function(s) dir table 14. 240-pin mqfp pin assignments (continued)
ds581pp2 ? copyright 2002 cirrus logic (all rights reserved) 45 cs98200 next generation dvd processor 163 dac_agnd gnd analog ground 164 dac_a3v3 pwr analog power 3.3 v 165 dac_agnd gnd analog ground 166 dac_a3v3 pwr analog power 3.3 v 167 dac_a3v3 pwr analog power 3.3 v 168 dvdl_rdy b4 primary dvd control ready i (1.)gpio_dvd[16] (2.) secondary host slave chip_select b i 169 dig_1v8 pwr digital power 1.8 v 170 h_a_0 b4 host master address[0] o (1.) gpio_hst[16] (2.) primary host slave address[0] b i 171 dig_gnd gnd digital ground 172 h_a_1 b4 host master address[1] o (1.) gpio_hst[17] (2.) primary host slave address[1] b i 173 h_a_2 b4 host master address[2] o (1.) gpio_hst[18] (2.) primary host slave address[2] b i 174 dvd_d_0 b4 primary dvd data[0] i (1.) secondary video_in data[0] (2.) gpio_dvd[0] (3.) secondary host slave data[0] i b b 175 dvd_d_1 b4 primary dvd data[1] i (1.) secondary video_in data[1] (2.) gpio_dvd[1] (3.) secondary host slave data[1] i b b 176 h_a_3 b4 host master address[3] o (1.) gpio_hst[19] (2.) primary host slave address[3] b i 177 h_ale b4 host master address latch o gpio_hst[20] b 178 dvd_d_2 b4 primary dvd data[2] i (1.) secondary video_in data[2] (2.) gpio_dvd[2] (3.) secondary host slave data[2] i b b 179 dvd_d_3 b4 primary dvd data[3] i (1.) secondary video_in data[3] (2.) gpio_dvd[3] (3.) secondary host slave data[3] i b b 180 pll_1v8 pwr pll power 1.8 v 181 pll_gnd gnd pll ground 182 dvd_d_4 b4 primary dvd data[4] i (1.) secondary video_in data[4] (2.) gpio_dvd[4] (3.) secondary host slave data[4] i b b 183 dvd_d_5 b4 primary dvd data[5] i (1.) secondary video_in data[5] (2.) gpio_dvd[5] (3.) secondary host slave data[5] i b b pin # pin name type primary function dir secondary function(s) dir table 14. 240-pin mqfp pin assignments (continued)
46 ? copyright 2002 cirrus logic (all rights reserved) ds581pp2 cs98200 next generation dvd processor 184 dvd_d_6 b4 primary dvd data[6] i (1.) secondary video_in data[6] (2.) gpio_dvd[6] (3.) secondary host slave data[6] i b b 185 dvd_d_7 b4 primary dvd data[7] i (1.) secondary video_in data[7] (2.) gpio_dvd[7] (3.) secondary host slave data[7] i b b 186 h_cs_0 b4 host master chip_select[0] o (1.) secondary dvd start sector (2.) gpio_hst[21] (3.) primary host slave chip select i b i 187 h_cs_1 b4 host master chip_select[1] o (1) secondary dvd error (2.) gpio_hst[22] i b 188 io_3v3 pwr io power 3.3 v 189 h_cs_2 b4 host master chip_select[2] o gpio_hst[23] b 190 io_gnd gnd io ground 191 h_cs_3 b4 host master chip_select[3] o gpio_hst[24] b 192 h_rd b4 host master read o (1.) secondary dvd ready (2.) gpio_hst[25] (3.) primary host slave read o b i 193 h_wr b4 host master write o (1.) secondary dvd data enable (2.) gpio_hst[26] (3.) primary host slave write i b i 194 h_rdy b4s host master ready i (1.) secondary dvd data strobe (2.) gpio_hst[27] (3.) primary host slave ready i b o 195 spi_clk b4s spi clock b gpio_mis[2] b 196 spi_do b4 spi data out/inout b gpio_mis[3] b 197 spi_di b4 spi data in i gpio_mis[4] b 198 spi_rdy b4 spi ready / chip select b gpio_mis[5] o 199 audi_d b4 pcm input data i gpio_mis[15] b 200 audi_lr b4 pcm lr clock i gpio_mis[16] b 201 audi_bck b4s pcm input clock i (1.) aud_pll_aux_fin[0] (2.) gpio_mis[17] (3.) audioout_mute i b o 202 dac_agnd gnd analog ground 203 dac_d1v8 pwr digital power 1.8 v 204 dac_dgnd gnd digital ground 205 ub_out anlg ub_out_1 206 dac_a3v3 pwr analog power 3.3 v pin # pin name type primary function dir secondary function(s) dir table 14. 240-pin mqfp pin assignments (continued)
ds581pp2 ? copyright 2002 cirrus logic (all rights reserved) 47 cs98200 next generation dvd processor 207 dac_agnd gnd analog ground 208 yg_out anlg yg_out_1 209 dac_a3v3 pwr analog power 3.3 v 210 dac_agnd gnd analog ground 211 vr_out anlg vr_out_1 212 dac_a3v3 pwr analog power 3.3 v 213 dac_agnd gnd analog ground 214 comp2 anlg compensation 215 iset2 anlg current set 216 vref2 anlg voltage ref 217 dac_agnd gnd analog ground 218 dac_a3v3 pwr analog power 3.3 v 219 dac_agnd gnd analog ground 220 dac_a3v3 pwr analog power 3.3 v 221 dac_a3v3 pwr analog power 3.3 v 222 audo_lr b4 pcm lr clock o (1.) clock_monitor_cpu (2.) host parslave_set o i 223 dig_1v8 pwr digital power 1.8 v 224 audo_bck b4 pcmo bclk o (1.) clock_monitor_drc (2.) gpio_mis[11] o b 225 dig_gnd gnd digital ground 226 aud_xclk b4s pcm mclk output o pcm mclk external input i 227 audo_d_1 b4 pcm data out[1] o (1.) system clock external input (2.) gpio_mis[12] i b 228 audo_d_2 b4 pcm data out[2] o (1.) cpu clock external input (2.) gpio_mis[13] i b 229 audo_d_3 b4 pcm data out[3] o (1.) aud_pll_aux_fin[1] (2.) gpio_mis[14] i b 230 io_3v3 pwr io power 3.3 v 231 xtlclk_i osc 27 mhz clock in i 232 xtlclk_o osc 27 mhz clock out o 233 io_gnd gnd io ground 234 audo_d_0 b4 pcm data out[0] o (1.) main_clock_monitor (2.) hostslave_par_i2c_sel o i pin # pin name type primary function dir secondary function(s) dir table 14. 240-pin mqfp pin assignments (continued)
48 ? copyright 2002 cirrus logic (all rights reserved) ds581pp2 cs98200 next generation dvd processor 235 spdif_o b4 spdif o process_monitor_out o 236 dvd_stb b4s primary dvd data strobe i (1.) host master address[4] (2.) gpio_dvd[8] o b 237 dvd_ena b4 primary dvd data enable i (1.) host master address[5] (2.) gpio_dvd[9] o b 238 dvd_sos b4 primary dvd start sector i (1.) host master address[6] (2.) gpio_dvd[10] o b 239 dvd_err b4 primary dvd error i (1.) host master address[7] (2.) gpio_dvd[11] o b 240 pll_gnd gnd pll ground pin # pin name type primary function dir secondary function(s) dir table 14. 240-pin mqfp pin assignments (continued)
ds581pp2 ? copyright 2002 cirrus logic (all rights reserved) 49 cs98200 next generation dvd processor 8. interface descriptions 8.1 sdram interface pins these pins are used to interface the cs98200 with some external sdram. the cs98200 can interface with sdram of various sizes. only 32-bit data width is supported. follow the instructions in tabl e 15 on how to interface with any particular configuration of sdram. 8.2 rom/nvram interface pins this is the interface to the non-volatile memory that contains the firmware. see tab le 16 . it could be either rom, nvram ? flash, or eeprom, or any combination of these types of memory. this interface can also connect to sram that would emulate a rom on a development system. the bus width is 8 bits. pin signal name type description 11,12,13,15,16, 17,18,20,21,23, 26,27,28,29,30, 32,61, 56, 55, 53, 51, 50, 49, 48, 47, 45, 42, 40, 39, 38, 37, 36, m_d[31:0] b memory data bus. cs98200 uses all 32 bits. 90, 89, 88, 87, 85, 82, 80, 79, 78, 77, 76 m_a[10:0] o memory address bus. connect in order starting with m_a[0] to all ram address pins not already connected to m_bs[ 1:0]_n or m_ap. 64 m_cko o memory clock 66 m_cke o memory clock enable 69 m_bs0_n o bank selection. always connect to ram bs or bs0 pin. 68 m_bs1_n o bank selection. always connect to ram bs or bs0 pin. 67 m_ap o memory auto pre-charge. always connect to ram ap pin. 70 m_ras_n o memory row address strobe 71 m_cas_n o memory column address strobe 73 m_we_n o memory write enable 62, 35, 33, 10 m_dqm[3:0] o io mask of data bus m_dqm[3] -> m_d[31:24] table 15. sdram interface pins pin signal name type description 91,92,93,94,95, 96,99,101 nv_d[7:0] b memory data bus. 90, 89, 88, 87, 85, 82, 80, 79, 78, 77, 76 m_a[10:0] o memory address bus[10:0] 32, 30, 29, 28, 27, 26, 23, 21, 20, 18, 17, 16 m_d[31:16] o memory address bus[23:11] 67 m_ap o output enable 73 m_we_n o write enable. table 16. rom/nvram interfa c e
50 ? copyright 2002 cirrus logic (all rights reserved) ds581pp2 cs98200 next generation dvd processor 8.3 video output interface pins this is the interface to a video encoder chip that will send the cs98200 video signals to a tv. see table 17 . this interface uses the same pins of the video input interface, so you are not able to use video input (primary) and video output (secondary) at the same time. . 8.4 video input interface pins see tab l e 18 . 74 nv_ce_n o rom/nvram chip enable. pin signal name type description 131s vout_clk o 27 mhz clock output. 129s vout_hs o horizontal sync. output when the cs98200 is the video master, input when the video encoder is master. 128s vout_vs o vertical sync. output when the cs98200 is the video mas- ter, input when the video encoder is master. 57s, 58s, 59s, 60s, 102s, 103s, 104s, 106s vout_d[7:0] o video data output[7:0] in cb, y, cr, y format. table 17. video output interface pin signal name type description 131 vin_clk i video input clock. 128 vin_vs i video input vertical sync. 129 vin_hs i video input horizontal sync. 57, 58, 59, 60, 102, 103, 104, 106 vin_d [7:0] i video data input[7:0] in cb, y, cr, y format. table 18. video input interface table 16. rom/nvram interface (continued)
ds581pp2 ? copyright 2002 cirrus logic (all rights reserved) 51 cs98200 next generation dvd processor 8.5 audio pcm interface pins this is the audio pcm interface that connects to an audio codec. see tabl e 19 . the sample rate and the size of the samples are programmable for both input and output direction. pin signal name type description 226 aud_xclk b audio 256x/384x clock input or output to se rial dac. when output, is generated from cs98200 internal pll. 224 audo_bck o audio bit clock output to serial dac. 222 audo_lr o audio out left/right clock to serial dac. 234 audo_d_0 o audio serial data out[0]. 227 audo_d_1 o audio serial data out[1]. 228 audo_d_2 o audio serial data out[2]. 229 audo_d_3 o audio serial data out[3]. 235 spdif_o o s/pdif output 201 audi_bck i audio input bit clock. the cs98200 can be programmed to use the audio output function ? s internally generated bit clock, in which case this pin is not required. 200 audi_lr i audio input left/right clock. the cs98200 can be pro- grammed to use the audio output function ? s internally gen- erated lr clock, in which case this pin is not required. 199 audi_d i audio input data from serial adc. table 19. pcm audio interfa c e
52 ? copyright 2002 cirrus logic (all rights reserved) ds581pp2 cs98200 next generation dvd processor 8.6 host master/atapi interface pin signal name type description 186, 187, 189, 191 h_cs[3:0] o host chip select[3:0]. the host master can be pro- grammed to use a different protocol for each of the 4 chip selects 177 h_ale o host address latch enable. used for m odes which multiplex upper address information onto the data lines 192 h_rd o host read request. 193 h_wr o host write request. 194 h_rdy i host ready. connect to pull-up or pull-down if host is not used. 170, 172, 173, 176 h_a[3:0] o host address[3:0]. 123, 124, 125, 126, 127, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143 h_d[15:0] b host data bus[15:0]. these pins can also output host address during the address phase for multi- plexed address/data m ode. tie together to pull-up or pull-down if host is not used. table 20. host master/atapi interface
ds581pp2 ? copyright 2002 cirrus logic (all rights reserved) 53 cs98200 next generation dvd processor 8.7 dvd loader interface this interface connects to standard dvd loaders, and consists of three parts: control, dvd data and cd data. (see tab le 21 .) this interface shares cs98200 pins with the host master/atapi interface. (see table 20 on page 52 .) the definition of the pins is set via register programming, and the two modes are mutually exclusive. 8.8 dvd serial data interface this interface conne cts to the data port of low cost dvd loaders using a 4-wire serial interface. in this case, control for the loader will typically be done using the 2-wire serial interf ace master. the atapi/io cha nnel pins are then free to be used for a second dvd loader, a general purpose atapi, or as gpios. pin signal name type description 174, 175, 178, 179, 182, 183, 184, 185 dvd_d[7:0] i primary dvd data 168 dvdl_rdy i primary dvd control ready 236 dvd_stb i primary dvd data strobe 237 dvd_ena i primary dvd data enable 238 dvd_sos i primary dvd start sector 239 dvd_err i primary dvd error 116 dvd_rdy o primary dvd data request 117 dvdl_di i primary dvd control data in 118 dvdl_do o primary dvd control data out 119 dvdl_ck o primary dvd control clock 144 cd_bclk i primary cd bit clock 145 cd_lrck i primary cd l/r clock 146 cd_data i primary cd data 147 cd_c2po i primary cd c2p0 table 21. dvd i/o channel interface pin signal name type description 144s /141s dvds_clk i dvd clock input 146s/143s dvds_data i dvd serial data input (data can be input msb or lsb first) 147s/140s dvds_vld i dvd valid ( a bit of data is clocked in when this pin is high) 145s/142s dvds_sos i dvd start of sector input
54 ? copyright 2002 cirrus logic (all rights reserved) ds581pp2 cs98200 next generation dvd processor 8.9 spi interface the spi interface supports industry standard 3-wire protocols. (see tab le 22 ) in master mode, this interface can control a front panel or a small non-volatile memory. in slave mode, it can operate un- der control of an external processor, for example, in a combination unit. 8.10 general purpose input/output (gpio) the cs98200 provides enough gpio pins, each with individual output high-z-state controls. high- z-state means that the output driver is turned off or placed in the high-impedance state. tabl e 23 describes the general purpose i/o interface. additional pins may also be re-defined as gpios. pin signal name type description 195 spi_clk b spi clock 196 spi_do b spi data in/out 197 spi_di i spi data in 198 spi_rdy b spi ready / chip select table 22. spi interface pin signal name type description 174s, 175s, 178s, 179s, 182s, 183s, 184s, 185s, 236s, 237s, 238s, 239s, 116s, 117s, 118s, 119s, 168s, 144s, 145s, 146s, 147s, gpio_dvd[20:0] b 21 general purpose i/os 123s, 124s, 125s, 126s, 127s, 133s, 134s, 135s, 136s, 137s, 138s, 139s, 140s, 141s, 142s, 143s, 170s, 172s, 173s, 176s, 177s, 186s, 187s, 189s, 191s, 192s, 193s, 194s gpio_hst[0:27] b 28 general purpose i/os 57s, 58s, 59s, 60s, 102s, 103s, 104s, 106s, 128s, 129s, 131s, gpio_vis[0:10] b 11 general purpose i/os 109s, 110s, 125s, 126s, 127s, 198s, 111s, 112s, 113s, 114s, 115s, 224s, 227s, 228s, 229s, 199s, 200s, 201s, 5s, 6s, 7s, 8s gpio_mis[0:21] b 22 general purpose i/os table 23. general purpose i/o interface
ds581pp2 ? copyright 2002 cirrus logic (all rights reserved) 55 cs98200 next generation dvd processor 8.11 uart interface pins the cs98200 has two 16550-type uarts for rs-232 serial communications, both of which have two 16-byte fifos for receiving and transm itting data. 8.12 i 2 c interface the i 2 c pins are used for both master and slave mode. 8.13 miscellaneous interface pins these pins are used for used for basic functions such as clock and reset input. see tab le 26 . pin signal name type description 111 txd_1 o uart1 tx data 112 rxd_1 i uart1 rx data 113 txd_2 o uart2 tx data 114 rxd_2 i uart2 rx data table 24. uart interface pins pin signal name type description 107 scl1 b i 2 c debug slave 108 sda1 b i 2 c debug slave 109 scl2 b i 2 c master/simple slave 110 sda2 b i 2 c master/simple slave table 2 5. i 2 c interface pins pin signal name type description 4 ir_in i infrared input, from ir receiver. 231 xtlclk_i i 27 mhz clock input. 232 xtlclk_o o 27 mhz clock output. 2 rst_n i reset input, active low. 3 test i manufacturing test pin, should always c onnect to gr ound. table 26. miscellaneous interface pins
56 ? copyright 2002 cirrus logic (all rights reserved) ds581pp2 cs98200 next generation dvd processor 8.14 power and ground the cs98200 requires 4 different types of power supplies ? plls, digital, analog, and io pins -. the plls and digital power use 1.8 v power supply. the io pins and digital power use 3.3 v power sup- ply, and are 5 v input tolerant. (see table 27. ) pin signal name type description 1, 120, 180, pll_1v8 2.5 v for internal plls 149, 203 dac_d1v8 digital power 1.8 v 152, 155, 158, 164, 166, 167, 206, 209, 212, 218, 220, 221 dac_a3v3 analog power 3.3 v 9, 19, 31, 41, 54, 65, 75,86, 105, 130, 188, 230 io_3v3 3.3 v for i/os 22,46, 81, 100, 169, 223 dig_1v8 digital power 150, 204 dac_dgnd digital ground 148,153, 156, 159, 163, 165, 202, 207, 210, 213, 217, 219 dac_agnd analog ground 121, 181, 240 pll_gnd ground for internal plls 14, 25, 34, 43, 52, 63, 72, 84, 97, 122, 132, 190, 233 io_gnd ground for i/os 24, 44, 83, 98, 171, 225 dig_gnd digital ground table 27. power and ground
ds581pp2 ? copyright 2002 cirrus logic (all rights reserved) 57 cs98200 next generation dvd processor 9. 240-pin mqfp package specifications notes: 1) dimensions are in millimeters, and controlling dimension is millimeter. 2) package body dimensions do not include mold protrusion, which is 0.25 mm (0.010 in). 3) pin 1 identi t cation may be either ink dot or dimple. 4) package top dimensions can be smaller than bottom dimensions by 0.20 mm (0.008 in). 5) the ? lead width with plating ? dimension does not include a total allow ab le dambar protrusion of 0.08 mm (at maximum material condition). 6) ejector pin marks in molding are present on every package. 7) drawing above does not re ? ect exact package pin count. 3.20 3.60 0 min 7 max 0.25 min pin 1 indicator 34.35 34.85 0.10 0.30 31.90 32.10 0.50 typ 34.35 34.85 31.90 32.10 0.16 4.10 0.40 0.60 pin 1 pin 240 max typ figure 25. 240-pin mqfp package drawing
58 ? copyright 2002 cirrus logic (all rights reserved) ds581pp2 cs98200 next generation dvd processor 10. conventions this section presents acronyms, abbreviations, units of measurement, and conventions used in this data sheet. 10.1 acronyms and abbreviations table 28 lists abbreviations and acronyms used in this data sheet. acronym/ abbreviation definition a/d analog-to-digital adc analog-to-digital converter codec coder / decoder d/a digital-to-analog dma direct-memory access epb embedded peripheral bus fcs frame check sequence fifo first in / first out fiq fast interrupt request gpio general purpose i/o ict in circuit test ir infrared irq standard interrupt request irda infrared data association jtag joint test action group lcd liquid crystal display led light-emitting diode mqfp medium profile quad flat pack lsb least significant bit mips millions of instructions per second mmu memory management unit msb most significant bit pbga plastic ball grid array pcb printed circuit board pda personal digital assistant pll phase locked loop p/u pull-up resistor risc reduced instruction set computer rtc real-time clock sir slow (9600 ? 115.2 kbps) infrared sram static random access memory ssi synchronous serial interface table 28. acronyms and abbreviatio ns
ds581pp2 ? copyright 2002 cirrus logic (all rights reserved) 59 cs98200 next generation dvd processor 10.2 units of measurement 10.3 general conventions hexadecimal numbers are presented with all letters in uppercase and a lowercase ? h ? appended or with a 0x at the beginning. for example, 0x14 and 03cah are hexadecimal numbers. binary num- bers are enclosed in single quotation marks when in text (for example, ? 11 ? designates a binary num- ber). numbers not indicated by an ? h ? , 0x or quotation marks are decimal. registers are referred to by acronym, with bits listed in brackets separated by a colon (:) (for exam- ple, codr[7:0]), and are described in the cs98200 registers document . the use of ? tbd ? indicates values that are ? to be determined, ? ? n/a ? designates ? not available, ? and ? n/c ? indicates a pin that is a ? no connect. ? tap test access port tlb translation lookaside buffer uart universal asynchronous receiver symbol unit of measure c degree celsius fs sample frequency hz hertz (cycle per second) kbps kilobits per second kb kilobyte (1,024 bytes) khz kilohertz k ? kilo ohm mbps megabits (1,048,576 bits) per second mb megabyte (1,048,576 bytes) mbps megabytes per second mhz megahertz (1,000 kilohertz) a microampere fmicrofarad wmicrowatt s microsecond (1,000 nano seconds) ma milliampere mw milliwatt ms millisecond (1,000 microseconds) ns nanosecond vvolt wwatt table 29. units of measurement acronym/ abbreviation definition table 28. acronyms and abbreviations (continued)
60 ? copyright 2002 cirrus logic (all rights reserved) ds581pp2 cs98200 next generation dvd processor 10.4 pin description conventions abbreviations used for signal directions are listed in table 30 . pin numbers that have an ? s ? after the pin number indicate that the pin is using a secondary function for that pin . 11. ordering information legend here is the legend for understanding the ordering information listed above. note: go to the cirrus logic internet site at http://cirrus.com/corporate/contacts to find contact information for your local sa les representative. abbreviation direction i input o output b input or output table 30. pin description conventions cs98200 ? cv ? xx product line: embedded processor part number temperature range: package type: v = low profile quad flat pack (240-pin lqfp) b = plastic ball grid array (17 mm x 17 mm) (256-ball pbga) r = reduced ball grid array (13 mm x 13 mm) (204-pin t fbga) c = commercial e = extended operating version i = industrial operating version processor speed m = medium profile quad flat pack (240-pin mqfp)

▲Up To Search▲

Price & Availability of CS98200-EB

	To Download CS98200-EB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .